1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method of conducting two cutting process to form gate trenches within a gate line after replacement metal gate (RMG) process.
2. Description of the Prior Art
With increasing miniaturization of semiconductor devices, it is crucial to maintain the efficiency of miniaturized semiconductor devices in the industry. However, as the size of the field effect transistors (FETs) is continuously shrunk, the development of the planar FETs faces more limitations in the fabricating process thereof. On the other hand, non-planar FETs, such as the fin field effect transistor (Fin FET) have three-dimensional structure, not only capable of increasing the contact to the gate but also improving the controlling of the channel region, such that the non-planar FETs have replaced the planar FETs and become the mainstream of the development.
The current method of forming the Fin FETs is forming a fin structure on a substrate primary, and then forming a gate on the fin structure. The fin structure generally includes the stripe-shaped fin formed by etching the substrate. However, under the requirements of continuous miniaturization, the width of each fin, as well as the pitch between fins have to be shrunk accordingly. Thus, the fabricating process of the Fin FETs also faces more challenges and limitations. For example, gate lines formed between adjacent fin-shaped structures have the tendency to be tangled due to smaller pitch. The entanglement of the gate lines, and more particularly the uneven thickness of the work function metal layer within the gate line typically results in instability of Vt of the device. Hence, how to resolve the issue has become an important task in this field.